1. Field of the Invention
This invention relates to a semiconductor device comprising copper interconnects and a manufacturing process therefor.
2. Description of the Prior Art
Recent higher integration in a semiconductor device has increasingly required an interconnect layer having a lower resistance. Copper which is highly resistant to electromigration has been, therefore, widely used as an interconnect material. Copper as an interconnect material cannot be, however, anisotropically etched by RIE (Reactive Ion Etching), and thus is generally subject to a damascene process employing CMP (Chemical Mechanical Polishing). A conventional process for forming copper interconnects using CMP will be described with reference to FIG. 16.
As illustrated in FIG. 16(a), on a silicon substrate 1 are sequentially formed a silicon nitride film 2 with a thickness of 100 nm and a silicon oxide film 3 with a thickness of 1000 nm. Then, in the silicon oxide film 3 are formed by dry-etching a plurality of concaves reaching to the silicon nitride film 2.
Subsequently, as shown in FIG. 16(b), over the whole surface is deposited by sputtering a barrier metal film 4 consisting of Ta and TaN with a thickness of 20 nm. On the surface is then deposited by sputtering a seed metal film consisting of copper for growing copper plating (not shown). The substrate is immersed in an aqueous solution of cupric sulfate and is subsequently subject to electrolytic plating to form a copper film 5 and then annealing. The copper film 5 has a thickness of about 900 nm in its flat area. It is shown in FIG. 16(a).
Then, the copper film 5 is polished by CMP to level the substrate surface. CMP is generally performed using a polishing apparatus as shown in FIG. 17. Herein, a substrate 1 on which a film or films are formed as described above is referred to as a wafer 10. The wafer 10 is placed on the lower face of a wafer carrier 11. While the surface of the wafer 10 on which a film is to be formed is in contact with a polishing pad 12, both of the wafer carrier 11 and the polishing pad 12 are rotated at a certain rate. A polishing liquid 14 is supplied from an inlet 13 by a pump 15 between the wafer 10 and the polishing pad 12. The polishing liquid 14 may be generally a slurry in which an abrasive such as alumina and silica particles is dispersed
After exposing the barrier metal film 4 (FIG. 16(c)), the wafer is further polished to be as shown in FIG. 16(d) to form damascene interconnects.
The above process of the prior art may, however, often cause dishing and/or erosion, resulting in a dispersed resistance as it increases. It will be described below in detail.
Dishing will be first described. In the CMP step in FIG. 16(c), it is necessary to ensure an adequate polishing time to avoid remaining of the barrier metal film 4 on the silicon oxide film 3. The copper film 5 is polished substantially faster than the barrier metal film 4. For example, copper is polished by CMP usually 30 times or more as fast as a Ta family metal generally used as a barrier metal film. Consequently, as illustrated in FIG. 16(c), in a process after exposing the barrier metal film 4, the copper film 5 is excessively polished in relation to the barrier metal film 4 to provide a shape as shown in FIG. 19 in which the center of the copper film 5 is concaved. The phenomenon is referred to as xe2x80x9cDishingxe2x80x9d. Excessive polishing is required to a certain extent for substantially completely removing the barrier metal film 4 on the insulating film 3, generally leading to a certain extent of dishing. Such dishing in the copper film may cause local increase of an interconnect resistance. In addition, it may cause electromigration, leading to a less reliable device.
Next, erosion will be described. As described above, the CMP step in FIG. 16(c) requires a certain period of over polishing. The copper film 5 is polished considerably faster than the barrier metal film 4 or the silicon oxide film 3. It, therefore, causes a CMP rate between a dense interconnect area and an isolated interconnect area during the CMP step after exposing the barrier metal film 4. Specifically, in the dense interconnect area comprising many damascenes in the copper film 5, a relatively higher pressure is applied to the barrier metal film 4 and the silicon oxide film 3, in comparison with the isolated interconnect area comprising less damascenes in the copper film 5. Consequently, CMP may excessively proceed in the dense interconnect area, resulting in the surface concave as illustrated in FIG. 16(d). The phenomena is called xe2x80x9cerosionxe2x80x9d.
Erosion as described above degrades flatness of the substrate surface. Flatness may be more significantly degraded in a multilayer structure to cause significant problems such as short-circuit in interconnects and an increased interconnect resistance due to a reduced cross-section when forming damascene interconnects.
As described above, dishing and erosion are due to the polishing-rate difference between the metal and the barrier metal or the insulating film. In a practical manufacturing process, they are further accelerated by process factors, which will be described below.
FIG. 18 shows a wafer surface when a polishing liquid is supplied. The wafer and a polishing pad are rotated at the substantially same rate in the same direction. When polishing is conducted in such a situation, the periphery of the wafer whose peripheral velocity is higher than that of its inside becomes in contact with more pad surfaces per unit of time. The periphery, therefore, tends to be excessively polished in relation to the inside. In addition, there occurs uneven distribution of the polishing liquid between the periphery and the inside of the wafer surface. The polishing liquid applied dropwise to the polishing pad moves from the periphery to the inside of the wafer to be distributed on the whole surface of the wafer. In the light of the process, a time-mean concentration of the polishing liquid is higher in the periphery than in the inside. It also contributes to excessive polishing of the periphery in comparison with the inside. Furthermore, a wafer comprising metal and/or insulating films is bent with the film side being concaved. Therefore, when the wafer is pushed against the polishing pad 12 for polishing, the above curvature remains to a certain extent, so that the periphery tends to be more polished.
As described above, the wafer periphery is likely to be excessively polished in relation to the inside due to the process factors. A longer over-polishing time is, therefore, required for completing leveling over the whole surface of the wafer. Consequently, dishing and erosion become more prominent.
Such prominent dishing or erosion reduces a film thickness of copper interconnects while increasing an interconnect resistance. Furthermore, a difference in a film thickness becomes larger between copper interconnects, leading to a larger dispersion in an interconnect resistance. Such a difference in a film thickness is particularly significant between the periphery and the inside of the wafer.
Copper interconnects are generally formed by a so-called damascene process employing CMP. In the process, dishing and erosion described above are technically significant problems. To solve these problems, a variety of investigations have been attempted for improving the CMP process; particularly in terms of selection of a polishing liquid and a detection method for a polishing endpoint. However, none of these attempts have been adequately effective to prevent dishing or erosion.
In the light of the above situation, an objective of this invention is to prevent dishing and erosion during forming damascene interconnects and to prevent increase and dispersion in an interconnect resistance.
Previous attempts to prevent dishing and erosion have been mainly conducted in terms of improvement in a CMP process. On the other hand, according to this invention, a layout of copper interconnects in a horizontal direction is controlled to prevent dishing and erosion. Prevention of dishing and erosion by devising the interconnect layout has been hardly investigated. Our investigation has indicated that dishing and erosion can be effectively prevented by adjusting an interconnect occupancy and/or a line/space ratio to values within ranges different from those in a conventional interconnect design. This invention is based on these observations. This invention will be described.
This invention provides a semiconductor device comprising an interconnect layer where copper interconnects are buried in a concave in an insulating film via a barrier metal film, wherein the interconnect occupancy of the interconnect layer is 10 to 60%.
This invention also provides a process for manufacturing a semiconductor device comprising the steps of depositing an insulating film on a semiconductor substrate surface including a device-forming area and then forming a concave in the insulating film within the device-forming area; depositing a barrier metal film in the concave and forming a copper film to fill the concave; and removing the copper film formed in the area outside the concave by chemical mechanical polishing to form copper interconnects, wherein the interconnect occupancy of the copper interconnects in the device-forming area is 10 to 60%.
Investigations for a semiconductor device have been conventionally conducted for improving an interconnect occupancy, aiming at a highly integrated device. On the contrary, in this invention, an interconnect occupancy is as low as 10 to 60%, which allows dishing and erosion to be effectively prevented when an interconnect layer is formed by a process employing CMP. A CMP process has a variety of advantages for forming copper interconnects because it can pattern copper, a less etchable material, by a relatively convenient procedure. The manufacturing process for a semiconductor device according to this invention can solve the problems of dishing and erosion in such a CMP process, leading to a high-quality and high-productivity process. The semiconductor device according to this invention has a particular structure wherein the interconnect occupancy is within the above range, so that dishing and erosion can be minimized when using a CMP process advantageous for forming copper interconnects, a resistance value can be stable, and a productivity can be satisfactory.
This invention also provides a semiconductor device comprising an interconnect layer where copper interconnects are buried in a concave in an insulating film via a barrier metal film, wherein the interconnect layer comprises an interconnect area in which a plurality of copper interconnects are extended over 100 xcexcm or more in one direction and an average line/space ratio in the copper interconnects in the interconnect area is 4.5 or less.
This invention also provides a process for manufacturing a semiconductor device comprising the steps of depositing an insulating film on a semiconductor substrate surface including a device-forming area and then forming a plurality of concaves extending over 100 xcexcm or more in one direction within the device-forming area; depositing a barrier metal film in the concave and forming a copper film to fill the concave; and removing the copper film formed in the area outside the concave by chemical mechanical polishing to form a plurality of copper interconnects, wherein an average line/space ratio in the interconnect area is 4.5 or less.
An interconnect layer often comprises an interconnect area where a plurality of copper interconnects extend over 100 xcexcm or more in one direction (hereinafter, referred to as xe2x80x9carea (a)xe2x80x9d) and an area where a plurality of copper interconnects extend in two or more directions (hereinafter, referred to as xe2x80x9carea (b)xe2x80x9d). This invention defines design criteria for area (a). We have conducted investigation, focusing on area (a) where a plurality of copper interconnects extend over 100 xcexcm or more in one direction and has finally observed that dishing and erosion can be more effectively prevented by setting unique design criteria to the area. This invention is based on the observation.
FIG. 1 shows an example of an interconnect layout in area (a). In the figure, an interconnect layer is formed on a silicon substrate 1 via a silicon nitride film. The interconnect layer has a configuration where a plurality of copper interconnects 7 are formed in the silicon oxide film 3. The copper interconnects 7 are mutually parallel and extend over 100 xcexcm or more in one direction. In practice, there is a barrier metal film (not shown) between the copper interconnects 7 and the insulating film 3. Area (a) having such a configuration generally constitutes a main part of an intracellular area in a memory cell or a core area in a logic IC such as a CPU.
FIG. 2 shows an example of an interconnect layout in area (b). The interconnect layer comprises wider main interconnects 7a (VDD and VSS) and secondary interconnects 7b from the main interconnects to a diffusion layer 8, where the plurality of copper interconnects are vertically and horizontally disposed. In area (b), there is an area where copper interconnects extends in one direction, but their length is different from that in area (a), i.e., 20 xcexcm or less.